1. Field of the Invention
The present invention relates to a junction-isolated MOS integrated device.
2. Discussion of the Related Art
In integrated circuits of the above type, particularly those comprising LDMOS (Lateral Diffused Metal Oxide Semiconductor) transistors, each epitaxial pocket houses a respective device for isolating it electrically from adjacent devices and is surrounded by an isolating region extending from the surface of the integrated circuit to the substrate. The isolating region presents an opposite type of conductivity as that of the epitaxial pocket, and is so biased as to form, with the epitaxial pocket, a reverse-biased junction.
In circuits of this type, the gate, source and drain connections must be able to pass from the epitaxial pocket, over the isolating regions, without producing premature breakdown of the epitaxial pocket-isolating region junction, particularly in the two below-listed circuit configurations: "source-grounded", wherein the source region is grounded, the gate region presents a potential of a few volts, and the drain region presents a high potential relative to ground; and "source-follower", wherein the source, gate and drain regions present high potentials relative to ground (substrate).
Current technology provides for a maximum breakdown voltage approximately within the range 250-300 V, which thus represents the maximum voltage that can be used on the circuit.
It is an object of the present invention to provide an integrated device of the aforementioned type designed to ensure a higher breakdown voltage than currently available, and preferably of over 650 V.